1. Field of the Invention
The present invention relates to a code decoding apparatus, suitable for use in a communicating apparatus, a broadcasting apparatus, or an information apparatus, that performs a signal compressing process using a variable length code corresponding to a standard such as MPEG (Moving Picture Experts Group), JPEG (Joint Photographic Coding Experts Group), or the like.
2. Description of the Related Art
Recently, as digital signal processing technologies have advanced, many communication apparatuses, broadcasting apparatuses, and information apparatuses that are small and have high quality have been developed. In these devices, a signal compressing process is performed with variable length codes so as to compress the data of images, voice, and information.
Before explaining a conventional code decoding apparatus, with reference to FIG. 1, a signal sequence encoded with a variable length code will be briefly described. A signal sequence encoded with a variable length code is composed of a fixed length code 72, a specifically fixed length code 73, and a variable length code 74. Assuming that the entire code set is denoted by reference numeral 71, the relationship among the fixed length code 72, the specifically fixed code 73, and the variable length code 74 is shown in FIG. 1.
As shown in FIG. 1, the specifically fixed length code 73 is a part of the fixed length code 72. The specifically fixed length code 73 is independent from other codes. An unknown signal sequence can be uniquely detected by correlating it with a known specifically fixed length code. Thus, the specifically fixed length code 73 is mainly used for a synchronizing process and a syntax analyzing process. In addition, the variable length code 74 is a code based on a variable length encoding theorem. Since the code length of the variable length code 74 is variable, information can be compressed.
FIGS. 2 and 3 show an example of the structure of a conventional code decoding apparatus. FIG. 3 shows an example of the structure of a decoding unit shown in FIG. 2. In FIG. 3, similar portions to those in FIG. 2 are denoted by similar reference numerals. An encoded signal sequence received from a communication apparatus, a broadcasting apparatus, a storing medium, or the like is input to a buffer memory 75 through an input terminal 1. The encoded signal sequence that has been successively input is written to the buffer memory 75. When the buffer memory 75 has stored the encoded signal sequence for a predetermined time period or stored a predetermined amount of the signal sequence, the buffer memory 75 supplies the encoded signal sequence to a decoding unit 76. The decoding unit 76 decodes the encoded signal sequence. The decoded signal sequence is obtained from an output terminal 99. In other words, the system shown in FIG. 2 varies a decoding speed while the transmission rate of a signal sequence received from a communication path or a storing unit is being kept constant.
The encoded signal sequence that is read from the buffer memory 75 is supplied to a correlating unit 77, a fixed length code reading unit 78, and a variable length code decoder 79 that compose the decoding unit 76 shown in FIG. 3. The correlating unit 77 detects a specifically fixed length code and generates control information from the detected specifically fixed length code. The control information is used for performing a synchronizing process and a syntax analyzing process. The control information generated by the correlating unit 77 is supplied to a sequencer 80.
A fixed length code is read by the fixed length code reading unit 78. The fixed length code reading unit 78 directly outputs the fixed length code. When necessary, the fixed length code reading unit 78 converts the fixed length code into another code. The output signal of the fixed length code reading unit 78 is supplied to one input terminal of a selector 81.
A variable length code is read by the variable length code decoding unit 79. The variable length code decoder 79 converts the variable length code to another equivalent code. In other words, the variable length code decoding unit 79 finds a set of a known variable length code group corresponding to an unknown signal, selects another code (for example, a fixed length code) with the code length corresponding to the variable length code, discards a signal for the code length of the unknown signal sequence, and outputs another equivalent code to the next stage. For the unknown signal sequence, the process for fining a set of a known variable length code group is repeated a number of times corresponding to predetermined syntax or until a specifically fixed length code is detected. The resultant signal is supplied to the other input terminal of the selector 81.
The sequencer 80 controls the selector 81 with the control information corresponding to syntax received from the correlating unit 77 so as to select an output signal of the fixed length code reading unit 78 or a decoded output signal of the variable length code decoding unit 79. An output signal of the selector 81 is obtained through an output terminal 83. At this point, a synchronization signal formed by the sequencer 80 is obtained through an output terminal 82.
The synchronization signal and the decoded signal are supplied to a processing unit on the next stage through the output terminal 82 and the output terminal 83, respectively. The processing unit on the next stage is composed of for example a microprocessor. The synchronization signal causes the microprocessor to synchronize and perform a predetermined process for the decoded signal.
The circuit portion that requires the highest processing capability in the above-described conventional code decoding apparatus is the variable length code decoding unit 79 that finds a set corresponding to a given signal sequence from a known variable length code group.
A sequence in operations of which the variable length code decoding unit 79 finds a particular variable length code from an encoded signal sequence and discards a signal for the length of the code length of the variable length code from the signal sequence depends on the preceding decoded result because the code length is variable. Thus, a parallel operation or a pipeline operation cannot be used for the variable length code decoding unit 79. Consequently, the operation speed and the process capability of the entire circuit depend on the total time necessary for each sequential process of the variable length code decoding unit 79.
Thus, to cause the conventional code decoding apparatus to speed up, the variable length code decoding unit should be formed of wired logic and ROM. In addition, redundant portions should be satisfactorily removed so as to shorten the operation time for each sequential process.
However, when wired logic and ROM are used, a general-purpose variable length code decoding unit cannot be provided. Thus, a variable length code decoder should be de designed for each new code. Even if the variable length code decoding unit operates at high speed, its speed is lower than a circuit that operates in parallel or in pipeline.